Those skilled in the art will recognize that PLAs are generally broken into two planes. Input signals are presented to an AND plane, which determines the products of the input signals to generate product terms. The product terms are presented to the OR plane, which will determine the sum of the product terms that were provided by the AND plane. The output of the OR plane is latched for use by other circuitry or fed back into an input of the AND plane. Accordingly, PLAs provide a sum-of-products based on available inputs. Any logic function can be expressed in a sum-of-products form, wherein each output is the sum of products of true or complementary inputs.
Conventionally, dynamic NOR gates have been used to implement both the AND plane and the OR plane. Dynamic logic gates are gates that employ a clock signal to activate a logic function, as opposed to static logic gates, in which the output is merely a function of the inputs. When dynamic NOR gates are used to implement both the AND and OR planes, the PLA structure is referred to as a NOR-NOR PLA structure. A portion of a typical NOR-NOR PLA structure is illustrated in FIG. 1. Those skilled in the art will recognize that a typical PLA will have many more inputs, primary logic gates, and the like. The PLA includes an AND plane 12, as well as an OR plane 14. Input signals or their complements, PLAIN(n) are buffered by buffers 16 and presented to any number of NOR gates 18, wherein each NOR gate 18 effectively provides a logical NOR of select PLA input signals PLAIN(n). The output of each NOR gate 18 provides an OR plane input signal ORIN(n) to the OR plane 14.
Each of the NOR gates 18 in the AND plane 12 is driven by a main PLA clock CLKPLA. The PLA clock CLKPLA also drives a specially configured NOR gate, which is referred to herein as a replica clock NOR gate 20. The replica clock NOR gate 20 receives the PLA clock CLKPLA and generates a replica clock CLKREP that is used to drive the OR plane 14, as will be described in greater detail below. The replica clock NOR gate 20 essentially provides a delayed version of the PLA clock CLKPLA, wherein the delay is theoretically sufficient to allow each of the other NOR gates 18 to provide an appropriate output to the OR plane 14 before the replica clock CLKREP reaches the OR plane 14. As will be highlighted below, this race condition is subject to failure, which results in an improper PLA output signal PLAOUT(x). Prior to illustrating the race condition, an overview of the respective NOR gates 18 and replica clock NOR gate 20 is provided.
Each NOR gate 18 and replica clock NOR gate 20 includes a set of NMOS field effect transistors (FETs) connected in parallel to form an OR gate. The NMOS FETs of the OR gate are labeled T1, T2, and T3, wherein the drains of each of the NMOS FETs T1-T3 are connected to form an OR node OR(n). The sources of the NMOS FETs T1-T3 are coupled to the drain of another NMOS transistor, which is referred to as a footer transistor T4. The gates of the NMOS FETs T1-T3 of the OR gate are driven by different PLA input signals PLAIN, while the gate of the footer transistor T4 is driven by the PLA clock CLKPLA. The source of the footer transistor T4 is connected to ground. The OR node OR(n) is coupled to VCC, which is represented by a horizontal bar, by a PMOS FET. This PMOS FET is referred to as a pre-charge transistor T5. The gate of the pre-charge transistor T5 is driven by the PLA clock CLKPLA.
In operation, assume that the PLA clock CLKPLA is initially low, which will leave the footer transistor T4 turned off and will turn on the pre-charged transistor T5. As such, the OR node OR(n) goes high. In particular, the drains and associated capacitance associated with transistors T1-T3 are charged to allow the OR node OR(n) to go high when the pre-charge transistor T5 turns on. Since the footer transistor T4 is off, transistors T1-T3 are allowed to remain high regardless of the PLA input signal PLAIN(n) that is being presented to the respective gates of the transistors T1-T3.
When the PLA clock CLKPLA goes high, the pre-charge transistor T5 will turn off, while the footer transistor T4 turns on. Thus, the sources of transistors T1-T3 are pulled to ground while the OR node OR(n) remains charged. If any of the PLA input signals PLAIN(n) are high, the transistor T1-T3 to which the PLA input signal PLAIN(n) is connected will turn on, because the gate of that transistor T1-T3 will be high while the source is pulled to ground via the footer transistor T4. Since the footer transistor T4 is on, the OR node OR(n) can discharge through the one or more transistors T1-T3 that are on and the footer transistor T4. As a result, the OR node OR(n) will transition from a high to a low. The signal on the OR node OR(n) is buffered by a buffer 22 in each of the NOR gates 18 to provide the OR plane input signal ORIN(n).
Another PMOS FET is coupled in parallel with the pre-charge transistor T5 between the OR node OR(n) and VCC. This PMOS FET is referred to as a keeper transistor T6, whose gate is driven by an inverter 24 having an input that is coupled to the OR node OR(n). The keeper transistor T6 is provided to maintain the charge on the OR node OR(n) when none of the PLA input signals PLAIN(n) are high. When any one of the PLA input signals PLAIN(n) is high, the OR node OR(n) is driven low, and the inverter 24 will drive the gate of the keeper transistor T6 high, thus turning off the keeper transistor T6 and allowing the OR node OR(n) to go low.
In a case where none of the PLA input signals PLAIN(n) are high, or in other words, all of the PLA input signals PLAIN(n) are low, transistors T1-T3 will not turn on, and the OR node OR(n) will remain high. When the OR node OR(n) is high, the inverter 24 will drive the gate of the keeper transistor T6 low, thus turning on the keeper transistor T6. As a result, the keeper transistor T6 will maintain the OR node OR(n) high.
Thus, when the PLA clock CLKPLA is high, the OR node OR(n) is either a) kept high by the keeper transistor T6, if none of the PLA input signals PLAIN are high, or b) discharged, if any of the PLA input signals PLAIN are high, through any of the transistors T1-T3 that are turned on and the footer transistor T4. Again, the footer transistor T4 is turned on when the PLA clock CLKPLA is high. When the PLA clock CLKPLA transitions from a high to a low, the footer transistor T4 is turned off and the pre-charged transistor T5 is turned on, thereby charging the OR node OR(n) to a high, wherein the process will repeat with each cycle of the PLA clock CLKPLA.
As noted, the replica clock NOR gate 20 is essentially the same as the NOR gates 18, with the exception that at least one of the transistors T1-T3 that provides OR node OR(REP) is always on. Generally, one of the gates of transistors T1-T3 is tied high, while the gates of the remaining transistors T1-T3 are tied to ground. As illustrated, transistor T1 is the transistor whose gate is tied high. The gates of transistors T2 and T3 are tied low. The goal of the replica clock NOR gate 20 is to impart a delay on the PLA clock CLKPLA before it is presented to the OR plane 14. To maximize this delay, the replica clock NOR gate 20 is configured to provide the slowest signal path for the PLA clock CLKPLA. An inverter 26 is employed to provide additional delay and re-invert the PLA clock signal from the inversion provided by transistor T1 and the footer transistor T4 of the replica clock NOR gate 20. Because the gate of transistor T1 is tied high, the OR node OR(REP) always discharges when the PLA clock CLKPLA transitions from a low to a high. The signal on the OR node OR(REP) is inverted by the inverter 26, buffered by the buffer 22, and presented to the OR plane 14 as the replica clock CLKREP.
In operation, each of the OR nodes OR(n) of the NOR gates 18 has to discharge, if it is going to discharge, before the replica clock CLKREP goes high. If any OR node OR(n) of a NOR gate 18 discharges after the replica clock CLKREP goes high, there will be a failure of the PLA. An analysis of the OR plane 14 will illustrate why it is important to ensure that the replica clock CLKREP is asserted high after all of the OR nodes OR(n) of all the NOR gates 18 have discharged, if they are going to discharge.
As illustrated, the OR plane 14 includes a NOR gate 28, which like the NOR gates 18, includes a series of NMOS transistors T7 and T8, which are connected in parallel. The drains of the transistors T7 and T8 are coupled to form an output node OROUT(x). The gates of the transistors T7 and T8 are driven by the outputs of corresponding NOR gates 18. The sources of the transistors T7 and T8 are coupled to the drain of a footer transistor T9. The gate of footer transistor T9 is driven by the replica clock CLKREP. When the replica clock CLKREP goes high, the sources of the transistors T7 and T8 are pulled low, thereby enabling the input signals ORIN(n) from the NOR gates 18 to be processed by transistors T7 and T8. If any of the OR plane input signals ORIN(n) are high while the replica clock CLKREP is high, the output node OROUT(x) will go low and be latched by an output latch 30 to provide the PLA output signal PLAOUT(x).
With reference to FIG. 2, a timing diagram is illustrated, where each of the OR plane input signals ORIN(n) goes low, if they are going low, before the replica clock CLKREP goes high. In this instance, the OR plane input nodes ORIN(n) go low at time t1, and the replica clock CLKREP subsequently goes high at time t2. In this instance, the OR plane output node OROUT(x) remains charged high, which results in the PLA output signal PLAOUT(x) being properly latched. Notably, the OR plane output node OROUT(x) is normally charged high using pre-charge circuitry, which is not illustrated, but may be similar to that employed by the NOR gates 18 in the AND plane 12.
Turning now to FIG. 3, a timing diagram is illustrated wherein the replica clock CLKREP goes high at time t1 before the OR plane input signal ORIN(n) goes low at time t3. When the replica clock CLKREP goes high and one of the OR plane input signals ORIN(n) has not yet transitioned from a high to a low, the gate of one of the transistors T7 and T8 is driven high. The source of the corresponding transistor T7 or T8 is pulled low through the footer transistor T9 in response to the replica clock CLKREP going high. As such, the OR plane output node OROUT(x) is improperly discharged, which will result in the OR plane output node OROUT(x) going low at time t2 and being latched to provide an improper PLA output signal PLAOUT(x).
As PLAs grow larger and operating speed increase, the race condition between the arrival of the replica clock CLKREP and the OR plane input signals ORIN(n) at the NOR gate 28 of the OR plane 14 becomes more unpredictable. As seen from the above, the speed of the NOR gates 18 of the AND plane 12 may vary based on how fast the OR node OR(n) discharges. The speed at which the OR node OR(n) discharges will vary based on the PLA input signals PLAIN(n). When process and temperature variables are also factored in, designers reach a point where it is virtually impossible to design a stable and reliable PLA employing a NOR-NOR PLA structure, which will always avoid failures due to the replica clock CLKREP arriving at the OR plane 14 prior to the OR plane input signals ORIN(n). As such, there is a need for a PLA architecture that avoids this potential race condition, regardless of scale, operating speeds, or input conditions.
Another issue associated with NOR-NOR PLA structures is the amount of leakage current required to charge the OR node OR(n) and maintain a charge on the OR node OR(n) when the PLA clock CLKPLA is asserted high and all of the PLA input signals PLAIN(n) are low. As the number of transistors T1-T3 in a given NOR gate 18 increases, the size of the keeper transistor T6, as well as the pre-charge transistor T5, must increase to supply sufficient current to charge and maintain a charge on the OR node OR(n). Once the leakage current in a NOR gate 18 reaches a certain level, the keeper transistor T6 will be insufficient to supply enough leakage current, or the keeper circuit will require more than one pull down transistor to provide sufficient leakage current.
Accordingly, there also is a need for a PLA structure that significantly reduces the leakage current associated with charging and maintaining a charge on the OR nodes OR(n) within the AND plane 12. In certain applications, there is a further need to reduce the leakage current associated with maintaining a charge on the OR plane output node OROUT(x) in the OR plane 14.